page 1 of 9 document no. 70-0255-02 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. rf1 rf2 v1 50 ? 50? cmos control driver esd esd v2 rfc esd the pe4251 is a harp?-enhanced absorptive spdt (single pole double throw) rf switch for use in general switching applications and mobile infrastructure. this device offers a flexible supply voltage of 3.3/5v, single-pin or complementary pin control inputs, and 4kv esd tolerance. it presents a simple alternative solution to pin diode and mechanical relay switches. peregrine?s harp? technology enhancements deliver high linearity and exceptional performance. it is an innovative feature of the ultracmos? process, providing performance superior to gaas with the economy and integration of conventional cmos. product specification spdt ultracmos? rf switch 10 ? 3000 mhz, absorptive product description figure 1. functional diagram pe4251 features ? harp-technology enhanced ? low insertion loss: 0.60 db @ 1000 mhz ? high isolation: 62 db @ 1000 mhz ? p1db typical: +30.5 dbm ? iip3 typical: +59 dbm ? fast switching time: 150 ns ? flexible supply voltage: 3.3 v 10% or 5.0 v 10% supply (see table 3) ? excellent esd protection: 4000 v hbm ? no blocking capacitors required ? single pin or complementary control inputs figure 2. package type 8-lead msop with exposed paddle table 1. target electrical specifications temp = 25c, v dd = 3.3 or 5.0 v notes: 1. device linearity will begin to degrade below 10 mhz. 2. note absolute maximum rating of p in = 27 dbm. parameter conditions min typical max units operation frequency 1 10 3000 mhz insertion loss (rf1/rf2) 10 mhz 0.55 0.60 db 1000 mhz 0.60 0.70 db 2000 mhz 0.75 0.85 db 3000 mhz 0.75 0.90 db isolation (rfc to rf1/rf2) 1000 mhz 61 62 db 2000 mhz 51 53 db 3000 mhz 42 43 db return loss 1000 mhz 26 db 2000 mhz 23 db 3000 mhz 22 db input 1 db compression 2 50 - 3000 mhz 30.5 dbm input ip3 50 - 3000 mhz, +18 dbm per tone, 5 mhz spacing 59 dbm switching time 50% ctrl to 10/90% rf 150 300 ns logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4251 page 2 of 9 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0255-02 ultracmos? rfic solutions table 2. pin descriptions electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. table 3. operating ranges note 3. all rf pins must be dc blocked with an external series capacitor or held at 0 v dc . figure 3. pin configuration (top view) pin no. pin name description 1 v2 this pin supports two interface options: single-pin control mode . a nominal 3- volt supply connection is required. complementary-pin control mode . a complementary cmos control signal to v1 is supplied to this pin. 2 v1 switch control input, cmos logic level. 3 rfc rf common port. 3 4 n/c or gnd no connect or ground 5 rf1 rf1 port. 3 6 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 7 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 8 rf2 rf2 port. 3 paddle gnd exposed ground paddle. ground for proper device operation exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. switching frequency the pe4251 has a maximum 25 khz switching rate. 4251 1 2 3 4 8 7 6 5 v2 v1 rfc n/c or gnd rf2 gnd gnd rf1 exposed ground paddle note 4. customer must choose either 3.3 v or 5.0 v power supply range table 4. absolute maximum ratings symbol parameter/conditions min max units v dd power supply voltage 3 5.5 v v i voltage on any control input -0.3 5.5 v t st storage temperature range -65 150 c p in rf input power (50 ? ) 27 dbm v esd esd voltage (hbm) 5 esd voltage (machine model) 4000 250 v note: 5. human body model (hbm, mil_std 883 method 3015.7) parameter min typ max units v dd power supply voltage 4 3.0 4.5 3.3 5.0 3.6 5.5 v v i dd power supply current v dd = v cntl = 3.3v v dd = v cntl = 5.0v 55 75 60 80 a a control voltage high 0.8 x v dd v control voltage low 0.2 x v dd v p in rf input power (50 ? ) 27 dbm t op operating temperature range -40 25 85 c t st storage temperature range -65 25 150 c moisture sensitivity level the moisture sensitivity level rating for the pe4251 in the 8-lead msop package is msl1. logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4251 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0255-02 www.psemi.com page 3 of 9 control logic input the pe4251 is a versatile rf cmos switch that supports two operating control modes; single-pin control mode and complementary-pin control mode. single-pin control mode enables the switch to operate with a single control pin (pin 2) supporting a +3.3 or 5.0-volt cmos logic input, and requires a dedicated +3.3 or 5.0-volt power supply connection (pin 1). this mode of operation reduces the number of control lines required and simplifies the switch control interface typically derived from a cmos processor i/o port. complementary-pin control mode allows the switch to operate using complementary control pins v1 and v2 (pins 2 & 1), that can be directly driven by +3.3 or 5.0-volt cmos logic or a suitable processor i/o port. this enables the pe4251 to operate in positive control voltage mode within the pe4251 operating limits. control voltages signal path pin 1 (v2) = v dd pin 2 (v1) = high rfc to rf1 pin 1 (v2) = v dd pin 2 (v1) = low rfc to rf2 table 5. single-pin control logic truth table table 6. complementary-pin control logic truth table control voltages signal path pin 1 (v2 ) = low pin 2 (v1) = high rfc to rf1 pin 1 (v2) = high pin 2 (v1) = low rfc to rf2 logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4251 page 4 of 9 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0255-02 ultracmos? rfic solutions evaluation kit figure 4. evaluation board layouts figure 5. evaluation board schematic peregrine specification 102/0408 peregrine specification 101/0337 notes: 4.3 er and 2.1mil cu thickness. 3. all transmision lines are: 33mil width, 10mil gaps, 28mil core dielectric to damage by electrostatic discharge (esd) 2. caution: 1. use 101-0337-02 pcb. contains parts and assemblies susceptible or gnd r1 dni c2 100pf 1 2 j3 smasm 1 2 j4 smasm 1 2 j5 smasm 1 2 j2 smasm c1 100pf 1 2 j6 smasm 2 v1 1 v2 3 rfc 6 gnds1 7 gnds2 8 rf2 4 n/c 5 rf1 u1 msop 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 9 9 j1 header 2 x 5 pin r2 0 ohm r3 0 ohm the spdt switch evaluation kit board was designed to ease customer evaluation of the pe4250 spdt switch. the rf common port is connected through a 50 ? transmission line to the bottom sma connector, j3. port 1 and port 2 are connected through 50 ? transmission lines to two sma connectors on either side of the board, j4 and j2. a through transmission line connects sma connectors j5 and j6. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed of a two metal layer fr4 material with a total thickness of 0.0322?. the bottom layer provides ground for the rf transmission lines. the transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.033?, trace gaps of 0.010?, dielectric thickness of 0.028?, copper thickness of 0.0021? and r of 4.3. j1 provides a means for controlling the dc inputs to the device. the second-to-bottom lower right pin (j1-3) is connected to the device v1 input. the second-to-top upper right pin (j1-7) is connected to the device v2 input. footprints for decoupling capacitors are provided on both v1 and v2 traces. it is the responsib ility of the customer to determine proper supply decoupling for their design application. removing these components from the evaluation board has not been shown to degrade rf performance. logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4251 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0255-02 www.psemi.com page 5 of 9 figure 9. isolation: rfc-rf @ 3.3 v figure 8. isolation: rfc-rf @ 25 c figure 6. insertion loss: rfc-rf @ 25 c figure 7. insertion loss: rfc-rf @ 3.3 v logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4251 page 6 of 9 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0255-02 ultracmos? rfic solutions figure 10. return loss at active port @ 25 c figure 11. return loss at active port @ 3.3 v logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4251 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0255-02 www.psemi.com page 7 of 9 figure 12. package drawing 4) the pe4251 uses seating plane option 2 8-lead msop with exposed paddle: 19-0134-01 logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4251 page 8 of 9 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0255-02 ultracmos? rfic solutions 8-lead msop with exposed paddle table 7. ordering information figure 14. tape and reel specifications pin1 order code part marking description package shipping method ek4251-01 pe4251-ek pe4251-08msop-ek evaluation kit 1 / box pe4251mli 4251 pe4251g-08msop-cut tape or loose green 8-lead msop, exposed paddle cut tape or loose pe4251mli-z 4251 pe4251g-08msop-2000c green 8-lead msop, exposed paddle 2000 units / t&r figure 13. top marking specification 4251 llll yww aaaa: product number, last 4 digits, exp. llll: last four digits of the assembly lot number yww: date code, last digit of the year and work week logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4251 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0255-02 www.psemi.com page 9 of 9 sales offices the americas peregrine semiconductor corporation 9380 carroll park drive san diego, ca 92121 tel: 858-731-9400 fax: 858-731-9499 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f-92380 garches, france tel: +33-1-4741-9173 fax : +33-1-4741-9173 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a cnf (customer notification form). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liabilit y for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos, harp, multiswitch and dune are trademarks of peregrine semiconductor corp. high-reliability and defense products americas san diego, ca, usa phone: 858-731-9475 fax: 848-731-9499 europe/asia-pacific aix-en-provence cedex 3, france phone: +33-4-4239-3361 fax: +33-4-4239-7227 peregrine semiconductor, asia pacific (apac) shanghai, 200040, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652 peregrine semiconductor, korea #b-2607, kolon tripolis, 210 geumgok-dong, bundang-gu, seongnam-si gyeonggi-do, 463-943 south korea tel: +82-31-728-3939 fax: +82-31-728-3940 peregrine semiconductor k.k., japan teikoku hotel tower 10b-6 1-1-1 uchisaiwai-cho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213 logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
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